Watch Xiao/RISC-CPU-8-bits-Verilog

Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。

Watch Xiao/awesome-dv

Awesome ASIC design verification

Watch Xiao/darkriscv

opensouce RISC-V implemented from scratch in one night!

Watch Xiao/RV32IC-RTL-modeling-and-Verification

Watch Xiao/tinyriscv forked from liangkangnan/tinyriscv

一个从零开始写的极简、非常易懂的RISC-V处理器核。

Watch Xiao/FPGA

FPGA