@x1jia
X1jia 暂无简介
一个RISC-V(RV64GC)指令集的周期驱动User-Mode模拟器
The formal verification of a RISC-V SBI firmware.
SepTran: An AI compiler framework that separates algorithm logic from hardware mapping, enabling "write once, deploy everywhere" for high-performance kernels.
FASE (FPGA-Assisted Syscall Emulation) for RV64 ISA
tilelang-tpu
AI Benchmark suite for estimating the performance of GPU, TPU, etc.