• 1
• 0
• 0

RSPwFPGAs/fpga_pcie_shell

• 1
• 1
• 1

RSPwFPGAs/virtio-fpga

A platform for emulating Virtio devices with FPGAs

• 1
• 0
• 0

RSPwFPGAs/spike

• 1
• 0
• 0

RSPwFPGAs/hpu_fpga

Homomorphic PU is a processor on homomorphically encrypted data, which is integrated with TFHE-rs and receives encrypted operands and a stream of instructions and executes these instructions.

• 1
• 0
• 0

RSPwFPGAs/concrete

Concrete: TFHE Compiler that converts python programs into FHE equivalent

• 1
• 0
• 0

RSPwFPGAs/hw_regmap

• 1
• 0
• 0

RSPwFPGAs/edalize

An abstraction library for interfacing EDA tools

• 1
• 0
• 0

RSPwFPGAs/tfhe-rs

TFHE-rs: A Pure Rust implementation of the TFHE Scheme for Boolean and Integer Arithmetics Over Encrypted Data.

• 1
• 1
• 0

RSPwFPGAs/ixy

Forked from emmericp/ixy A simple yet fast user space network driver for Intel 10 Gbit/s NICs written from scratch

• 1
• 0
• 0

RSPwFPGAs/rspwfpgas-TMMA

TMMA: A Tiled Matrix Multiplication Accelerator for Self-Attention Projections in Transformer Models, optimized for edge deployment on Xilinx KV260.

• 1
• 0
• 0

RSPwFPGAs/rspwfpgas-MatMul_SA

This project implements a hardware-accelerated matrix multiplication using High-Level Synthesis (HLS).

• 1
• 0
• 0

RSPwFPGAs/rspwfpgas-mx-systolic-fpga

MX Systolic Arrays on FPGAs

• 1
• 0
• 0

RSPwFPGAs/rspwfpgas-microxcaling

MX Pytorch Emulation Library

• 1
• 0
• 1

RSPwFPGAs/fpga-npu forked from mirrors_intel/fpga-npu

• 2
• 0
• 0

RSPwFPGAs/virtio-fpga-bridge

Virtio front-end and back-end bridge, implemented with FPGA.

• 1
• 0
• 0

RSPwFPGAs/open-source-eda-scripts

• 1
• 0
• 0

RSPwFPGAs/DPU-PYNQ

• 1
• 0
• 0

RSPwFPGAs/ReActNet

• 1
• 0
• 0

RSPwFPGAs/SkrSkr

• 1
• 0
• 0

RSPwFPGAs/SkyNet