# sverilogparse

**Repository Path**: zzdeps/sverilogparse

## Basic Information

- **Project Name**: sverilogparse
- **Description**: No description available
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2022-03-21
- **Last Updated**: 2022-09-17

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# sverilogparse: Structural Verilog Parser in Rust
This is a structural verilog parser written in Rust.

Similar project: https://github.com/OpenTimer/Parser-Verilog