# riscv_chisel_cpu

**Repository Path**: victor824/riscv_chisel_cpu

## Basic Information

- **Project Name**: riscv_chisel_cpu
- **Description**: A simple riscv32-cpu only support rv32i written in Chisel.
- **Primary Language**: Scala
- **License**: MIT
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2024-08-17
- **Last Updated**: 2024-08-17

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

#	Introduction
	This repo is about a simple cpu project, written in chisel and tested on FPGA. There are two kinds of cpu : one-stage cpu and 5-stages pipeline cpu. Both are tested and can be run on FPGA. Of Course, We add some pheripherals so that 


#	riscv_cpu