# concurrent-data-capture

**Repository Path**: lottefang/concurrent-data-capture

## Basic Information

- **Project Name**: concurrent-data-capture
- **Description**: Capture data from multiple ADCs concurrently using an FPGA. Stream the captured data out over ethernet + UDP. Tested on the Spartan 6 XC6SLX9, Wiznet W5500, and MCP3002 ADC.
- **Primary Language**: Verilog
- **License**: MIT
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 1
- **Forks**: 1
- **Created**: 2018-12-09
- **Last Updated**: 2024-08-23

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

No README documentation available for this project.