# Processor-UVM-Verification

**Repository Path**: haoanqi/Processor-UVM-Verification

## Basic Information

- **Project Name**: Processor-UVM-Verification
- **Description**: System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
- **Primary Language**: Verilog
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 4
- **Forks**: 0
- **Created**: 2021-06-29
- **Last Updated**: 2023-10-30

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# Processor-UVM-Verification
System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment