# RISCV-CPU

**Repository Path**: dongfenga/RISCV-CPU

## Basic Information

- **Project Name**: RISCV-CPU
- **Description**: RISCV CPU simulation created via Logisim
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 1
- **Created**: 2020-07-01
- **Last Updated**: 2020-12-19

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# RISCV-CPU
RISCV CPU simulation created via Logisim. 

This project provides a visual and functional representation of a standard computer CPU operating various RISC-V assembly instructions. 

Such a CPU supports basic arithmetic operations, in addition to bitwise operators and conditional branch offset instructions.