# cxl_type3_tests

**Repository Path**: caiwanli/cxl_type3_tests

## Basic Information

- **Project Name**: cxl_type3_tests
- **Description**: No description available
- **Primary Language**: Unknown
- **License**: GPL-2.0
- **Default Branch**: main
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2025-09-08
- **Last Updated**: 2025-09-08

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# cxl\_type3\_tests
This repository contains two parts:
1. **memo** -- a versatile benchmark for CXL-related memory behaviors and characterizations.
2. **caption** -- a performance tuning (based on memory page allocation) tool to maximize the system memory bandwidth utilazation in a CXL-enabled system.

They are the correpsonding artifacts of the paper `Demystifying CXL Memory with True CXL-Ready Systems and CXL Memory Devices (MICRO'23)`, the first research work of CXL memory characterization based on real CXL hardware devices. 

For the artifact evaluation configurations, please refer to [link to config repo](https://github.com/ece-fast-lab/cxl_type3_tests_ae)

### Contact

For any questions, please :e-mail: <yans3@illinois.edu>.

Thank you! :wink:


## [Related Publication](https://doi.org/10.1145/3613424.3614256)


```bibtex
@inproceedings {sun-memo,
author = {Sun, Yan and Yuan, Yifan and Yu, Zeduo and Kuper, Reese and Song, Chihun and Huang, Jinghan and Ji, Houxiang and Agarwal, Siddharth and Lou, Jiaqi and Jeong, Ipoom and Wang, Ren and Ahn, Jung Ho and Xu, Tianyin and Kim, Nam Sung},
title = {Demystifying {CXL} memory with genuine {CXL}-ready systems and devices},
booktitle = {Proceedings of the 48th IEEE/ACM International Symposium on Microarchitecture (MICRO'23)},
year = {2023},
}
```