# SoC-Gulp

**Repository Path**: binaTree/SoC-Gulp

## Basic Information

- **Project Name**: SoC-Gulp
- **Description**: SoC设计流程总结，主要包括项目初始化/git仓库管理/验证环境搭建/memory生成替换/FPGA环境构建/ASIC环境构建/signoff环境构建等flow
- **Primary Language**: TypeScript
- **License**: LGPL-3.0
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 3
- **Created**: 2020-08-07
- **Last Updated**: 2022-11-16

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# SoC-Gulp

This repository contains SoC build flow, such as git/verif/asic/mem/fpga...


## How to Quick verif

### Install [Verilg-Perl](https://github.com/veripool/verilog-perl)

### Install [NodeJS & npm](https://nodejs.org/en/download/)

### Checkout The Code
```
$ git clone https://gitee.com/korbenyuan/SoC-Gulp.git SoC-Gulp
$ cd SoC-Gulp

$ npm install

$ source sourceme.csh
$ cd ..
```

### Build The Project
```
# initial project
$ sulp init:project -p test_demo

$ cd test_demo
$ sulp init:repo

$ cd verif/demo/testcase/test

# set EDA tools

$ sulp run:vsim
$ sulp load:wave
```


### TODO
* 支持verilator仿真器
* 支持gtkwave 波形工具
* 支持iverilog仿真器
* 支持yosys
* 支持OpenRoad