From 9156eefa97e2a09844d8c1916d5947bd2f00b198 Mon Sep 17 00:00:00 2001 From: Dongyan Chen Date: Mon, 12 May 2025 17:19:24 +0800 Subject: [PATCH 1/2] [RUIYI-RV-REUSE] RISC-V: Minimal support for ssnpm, smnpm and smmpm extensions. This patch support ssnpm, smnpm, smmpm, sspm and supm extensions[1]. To enable GCC to recognize and process ssnpm, smnpm, smmpm, sspm and supm extensions correctly at compile time. [1]https://github.com/riscv/riscv-j-extension/blob/master/zjpm/instructions.adoc Changes for v5: - Fix the testsuite error in arch-50.c. Changes for v4: - Fix the code based on the commit id 9b13bea07706a7cae0185f8a860d67209308c050. Changes for v3: - Fix the error messages in gcc/testsuite/gcc.target/riscv/arch-46.c Changes for v2: - Add the sspm and supm extensions. - Add the check_conflict_ext function to check the compatibility of ssnpm, smnpm, smmpm, sspm and supm extensions. - Add the test cases for ssnpm, smnpm, smmpm, sspm and supm extensions. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::check_conflict_ext): New extension. * config/riscv/riscv.opt: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-ss-1.c: New test. * gcc.target/riscv/arch-ss-2.c: New test. Reference: https://code.openruyi.cn/risc-verse/toolchain/gcc/-/commit/870d34d08aece4690c5fbdcc6a942759bedad3f4 Reuse-Type: patch-directly-reuse --- gcc/common/config/riscv/riscv-common.cc | 36 ++++++++++++++++++++++ gcc/config/riscv/riscv.opt | 19 ++++++++++++ gcc/testsuite/gcc.target/riscv/arch-ss-1.c | 5 +++ gcc/testsuite/gcc.target/riscv/arch-ss-2.c | 15 +++++++++ 4 files changed, 75 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/arch-ss-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/arch-ss-2.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 1bbd4d9e1f7..72fa644fc1a 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -227,6 +227,10 @@ static const riscv_implied_info_t riscv_implied_info[] = {"ssstateen", "zicsr"}, {"sstc", "zicsr"}, + {"ssnpm", "zicsr"}, + {"smnpm", "zicsr"}, + {"smmpm", "zicsr"}, + {"svbare", "zicsr"}, {"xtheadvarith", "v"}, @@ -422,6 +426,12 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"ssstateen", ISA_SPEC_CLASS_NONE, 1, 0}, {"sstc", ISA_SPEC_CLASS_NONE, 1, 0}, + {"ssnpm", ISA_SPEC_CLASS_NONE, 1, 0}, + {"smnpm", ISA_SPEC_CLASS_NONE, 1, 0}, + {"smmpm", ISA_SPEC_CLASS_NONE, 1, 0}, + {"sspm", ISA_SPEC_CLASS_NONE, 1, 0}, + {"supm", ISA_SPEC_CLASS_NONE, 1, 0}, + {"svinval", ISA_SPEC_CLASS_NONE, 1, 0}, {"svbare", ISA_SPEC_CLASS_NONE, 1, 0}, {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1427,6 +1437,26 @@ riscv_subset_list::check_conflict_ext () error_at (m_loc, "%<-march=%s%>: zcf extension supports in rv32 only", m_arch); + if (lookup ("ssnpm") && m_xlen == 32) + error_at (m_loc, "%<-march=%s%>: ssnpm extension supports in rv64 only", + m_arch); + + if (lookup ("smnpm") && m_xlen == 32) + error_at (m_loc, "%<-march=%s%>: smnpm extension supports in rv64 only", + m_arch); + + if (lookup ("smmpm") && m_xlen == 32) + error_at (m_loc, "%<-march=%s%>: smmpm extension supports in rv64 only", + m_arch); + + if (lookup ("sspm") && m_xlen == 32) + error_at (m_loc, "%<-march=%s%>: sspm extension supports in rv64 only", + m_arch); + + if (lookup ("supm") && m_xlen == 32) + error_at (m_loc, "%<-march=%s%>: supm extension supports in rv64 only", + m_arch); + if (lookup ("zfinx") && lookup ("f")) error_at (m_loc, "%<-march=%s%>: z*inx conflicts with floating-point " @@ -1856,6 +1886,12 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = RISCV_EXT_FLAG_ENTRY ("svbare", x_riscv_sv_subext, MASK_SVBARE), RISCV_EXT_FLAG_ENTRY ("svnapot", x_riscv_sv_subext, MASK_SVNAPOT), + RISCV_EXT_FLAG_ENTRY ("ssnpm", x_riscv_ss_subext, MASK_SSNPM), + RISCV_EXT_FLAG_ENTRY ("smnpm", x_riscv_sm_subext, MASK_SMNPM), + RISCV_EXT_FLAG_ENTRY ("smmpm", x_riscv_sm_subext, MASK_SMMPM), + RISCV_EXT_FLAG_ENTRY ("sspm", x_riscv_ss_subext, MASK_SSPM), + RISCV_EXT_FLAG_ENTRY ("supm", x_riscv_su_subext, MASK_SUPM), + RISCV_EXT_FLAG_ENTRY ("ztso", x_riscv_ztso_subext, MASK_ZTSO), RISCV_EXT_FLAG_ENTRY ("xcvmac", x_riscv_xcv_subext, MASK_XCVMAC), diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index a7545628111..a66bc7848dc 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -472,6 +472,25 @@ Mask(SVBARE) Var(riscv_sv_subext) Mask(SVNAPOT) Var(riscv_sv_subext) +TargetVariable +int riscv_ss_subext + +Mask(SSNPM) Var(riscv_ss_subext) + +Mask(SSPM) Var(riscv_ss_subext) + +TargetVariable +int riscv_sm_subext + +Mask(SMNPM) Var(riscv_sm_subext) + +Mask(SMMPM) Var(riscv_sm_subext) + +TargetVariable +int riscv_su_subext + +Mask(SUPM) Var(riscv_su_subext) + TargetVariable int riscv_ztso_subext diff --git a/gcc/testsuite/gcc.target/riscv/arch-ss-1.c b/gcc/testsuite/gcc.target/riscv/arch-ss-1.c new file mode 100644 index 00000000000..8f95737b248 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-ss-1.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_ssnpm_smnpm_smmpm_sspm_supm -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-ss-2.c b/gcc/testsuite/gcc.target/riscv/arch-ss-2.c new file mode 100644 index 00000000000..f1d7724fcee --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-ss-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm -mabi=ilp32d" } */ +int foo() +{ +} +/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': ssnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': smnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': smmpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': sspm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': supm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': ssnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': smnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': smmpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': sspm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': supm extension supports in rv64 only" "" { target *-*-* } 0 } */ -- Gitee From 145d4214129dba0ae5f0f1c1d85699c05e6857ea Mon Sep 17 00:00:00 2001 From: Jin Ma Date: Mon, 15 Dec 2025 10:40:57 +0800 Subject: [PATCH 2/2] [RUIYI-RV-REUSE] RISC-V: Add minimal svade/ssccptr/sstvecd/sstvala/sscounterenw/ ssu64xl/sha extensions for RVA23S64 gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Likewise. Reference: https://code.openruyi.cn/risc-verse/toolchain/gcc/-/commit/e3f5eaf043d4fbc03407b238e919bf33589d26ef Reuse-Type: patch-directly-reuse --- gcc/common/config/riscv/riscv-common.cc | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 72fa644fc1a..ea730af69a7 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -437,6 +437,14 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0}, {"svpbmt", ISA_SPEC_CLASS_NONE, 1, 0}, + {"svade", ISA_SPEC_CLASS_NONE, 1, 0}, + {"ssccptr", ISA_SPEC_CLASS_NONE, 1, 0}, + {"sstvecd", ISA_SPEC_CLASS_NONE, 1, 0}, + {"sstvala", ISA_SPEC_CLASS_NONE, 1, 0}, + {"sscounterenw", ISA_SPEC_CLASS_NONE, 1, 0}, + {"ssu64xl", ISA_SPEC_CLASS_NONE, 1, 0}, + {"sha", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0}, {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0}, {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0}, -- Gitee