# risc-v_cpu_core

**Repository Path**: UnbalancedCat/risc-v_cpu_core

## Basic Information

- **Project Name**: risc-v_cpu_core
- **Description**: RV32IMA cpu core
- **Primary Language**: Verilog
- **License**: Not specified
- **Default Branch**: main
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2026-03-20
- **Last Updated**: 2026-03-20

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

No README documentation available for this project.